The invention relates generally to a method for fabricating a semiconductor device and, more specifically, to a technology of forming a floating body transistor used in a highly-integrated semiconductor device using a silicon-on-insulator (SOI) structure.
In many semiconductor device systems, a semiconductor memory device is configured to store data generated or processed in the device. For example, if a request from a data processor such as a central processing unit (CPU) is received, a semiconductor memory device may output data to the data processor from unit cells in the device, or the device may store data processed by the data processor to unit cells of an address transmitted with the request.
Although data storage capacity of semiconductor memory device has increased, the size of semiconductor memory device has not increased proportionally because various elements and components used for read or write operations in a semiconductor memory device have reduced in size. Accordingly, components and elements unnecessarily duplicated in the semiconductor memory device, such as transistors or wires, are combined or merged to decrease the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory device affects improvement of the degree of integration.
As an example of a semiconductor memory device, Dynamic Random Access Memory (DRAM) is a type of volatile memory device configured to retain data while a power source is supplied. The unit cell comprises a transistor and a capacitor. In the case of the unit cell having a capacitor, after the datum “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., the amount of the charge stored therein is reduced, because of both leakage currents generated at junction of the storage nodes and inherent characteristics of the capacitor. As a result, a refresh operation is periodically required on the unit cells so that data stored in the DRAM cannot be destroyed.
In order to prevent the reduction of charge, numerous methods for increasing capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node. Otherwise, a capacitor having a two-dimensional structure is changed to have a three-dimensional cylindrical structure or a trench structure, thereby increasing the surface area of both electrodes of the capacitor. However, as the design rule is reduced, the plane area where a capacitor can be formed is reduced, and it is difficult to develop materials constituting an insulating film in the capacitor. As a result, the junction resistance value of the storage node (SN) and the turn-on resistance value of the transistor in the unit cell are larger, and accordingly it is difficult to perform normal read and write operations, and refresh characteristics deteriorate.
To improve the above-described shortcomings, the unit cell may comprise a transistor having a floating body. Thus, the unit cell of the semiconductor memory device does not include a capacitor used for storing data, but stores data in a floating body of the transistor included in the unit cell.
FIG. 1 is a circuit diagram illustrating a cell array of a general semiconductor memory device that includes unit cells each configured as a floating body transistor without any capacitors.
As shown, each unit cell included in the cell array includes a floating body transistor without any capacitors. In the floating body transistor, a gate is connected to one of word lines WL0 to WL3, a source is connected to one of source lines SL0 to SL3, and a drain is connected to one of bit lines BL0 and BL1. Also, the cell array further includes a dummy word line formed between the unit cells.
FIG. 2 is a cross-sectional diagram illustrating the cell array of FIG. 1 formed over a semiconductor substrate.
As shown, the cell array is formed over a SOI substrate that includes a bottom silicon layer 201, a buried insulating film 202 and a top silicon layer 203. In the top silicon layer 203, a portion except for the silicon active region 210 is etched, and buried with a device isolation film 211. A first gate pattern that includes a first gate spacer 203 and a first gate electrode 204 is formed over the center of the silicon active region 210, a second gate pattern that include a second gate spacer 213 and a second gate electrodes 214 are located over the device isolation film 211. Herein, the first gate electrode 204 located over the silicon active region 210 corresponds to one of the word lines WL0 to WL3 shown in FIG. 1, and the second gate electrode 214 positioned over the device isolation film 211 corresponds to the dummy word line WL shown in FIG. 1.
A contact plug 205 is formed at both sides of the gate pattern located over the silicon active region 210. One side is connected to a bit line 209 through a bit line contact 208, and the other side is connected to a source line 207 through a source line contact 206. The bit line 209 and the source line 207 are formed at a different level and at an intersection with each other.
FIGS. 3 to 6c are diagrams illustrating the cell array shown in FIG. 2.
Referring to FIG. 3, the island-shaped silicon active regions 210 are arranged over the SOI substrate in row and column directions. The neighboring silicon active regions 210 arranged in the row direction share the first gate electrode 204 as the word line WL. Between the neighboring silicon active regions 210 arranged in the column direction, the second gate electrode 214 over the device isolation film is formed as the dummy word line WL.
Referring to FIG. 4a, a contact plug mask 224 covers a space between the neighboring silicon active regions 210 arranged in the row direction to form a contact plug. A conductive material is deposited over the silicon active region 210 exposed between the first and second gate electrodes 204 and 214. Referring to FIG. 4b, formations of the gate electrode 204 and the contact plug 205 over the silicon active region 210 are understandable to people skilled in the art.
As shown in FIG. 5a, the conductive material deposited over the silicon active region 210 remains as the contact plug 205. A source line contact 206 is formed over one of the two contact plugs 205 located over the silicon active region 210. Referring to FIG. 5b, the source line contact 206 is formed over one of the two contact plugs 205.
Referring to FIG. 6a, the bit line contact 208 is formed over the other of the two contact plugs 205. A source line is formed over the source line contact 206 in a word line (WL) direction. The bit line 209 is formed in the column direction of the silicon active region 210. Particularly, FIG. 6b shows when the source line 206 is formed over the source line contact 206, and FIG. 6c shows when the bit line contact 208 is formed over the contact plug 205.
In the case of the unit cell including the above-described floating body transistor, holes remain in the floating body out of hot carriers generated corresponding to positive voltages (VG>0, VD>0) through the word line and a ground voltage GND (0V) applied to the source. While the semiconductor memory device performs a read operation for outputting data stored in the unit cells, a voltage is first supplied to the word line to turn on a cell transistor and, then, whether holes remain in the floating body, i.e., which the datum stored in the floating body is “0” or “1”, is understood based on the amount and speed of current flowing from the source line to the bit line.
In the case of the unit cell of the above-described cell array, one of source/drain of the floating body transistor is connected to the source line 207 through the contact plug 205 and the source line contact 206. If a junction resistance between the source line 207 and the source line contact 206 or between the source line contact 206 and the one of source/drain is large, the amount and speed of current flowing through a channel of the floating body transistor can be determined based on the junction resistance rather than the amount of holes stored in the floating body. In this case, it is difficult to distinguish data values “0” from “1” stored in the floating body transistor, thereby degrading the operation of the semiconductor memory device.